Alpha: Soldermask MCP is coming soon. Rinzler net is in development, coming soon.

Where the parts go, and how the copper joins them.

A lab on placing and routing. The instrument is a pipeline from a prompt to a fab-ready board; the record is every route it has run.

Open the buildHow it works

A rendered two-layer board with a black solder mask: an ESP32-S3 module, a USB-C receptacle, a pin header, two buttons and the decoupling, with the soldermask mark in white silkscreen at one corner.
Prompt
“a USB-powered board with an ESP32 module and a status LED”
Board
68 × 37 mm, two layersground poured both sides
Parts
22, in 13 linesall in stock at JLCPCB, checked live
Copper
25 nets, 0 unrouted0.127 mm track and clearance, first attempt
Verdict
Passedone thermal spoke short of the two KiCad wants
Price
$37.50 for one$10.37 each for ten, 15 Sep 2026

the problem

A board is not finished when it looks finished.

It is finished when a router closes every net and the DRC finds nothing — and today that verdict usually comes back from the fab.

soldermask builds backwards from it. Every stage is judged by the router and by KiCad’s DRC before it is trusted, and reports what it could not do.

how it works

The pipeline is the instrument.

The same sequence behind the command line and the app.

  1. 01a prompt becomes parts and a netlist
  2. 02every part resolved against live JLCPCB stock
  3. 03the circuit checked, then simulated
  4. 04the board placed, both sides if the front runs out of room
  5. 05routed: A* first, freerouting if a net is left short
  6. 06ground poured, then KiCad’s own DRC
  7. 07Gerbers and assembly files written
  8. 08priced, with a verdict: passed, or what did not
The same board from directly above: the module at centre, the USB-C receptacle at the top-left edge, the header down the left, the buttons and passives to the right.
the same board, from above — as KiCad renders the files that go to the fab

the app

The instrument, with a designer at it.

Every picture below is the app on 16 September 2026 building the sentence on the hero as one real turn — a different board from the hero’s, because a model’s answer is never the same twice: 17 parts, 18 nets, 55 × 37 mm, passed, $21.76 for one. Nothing is mocked, and nothing the build said is cropped away.

01 · the turn

One sentence in. Eighteen steps out.

The prompt as typed. The model designs the circuit, then every stage runs with its clock — parts, simulation, placement, routing, fab files, stock, 3D models — and when the first build came back with an ERC error the model was shown the findings and revised it. 1m 47s, a minute and a half of it the model.

The reply says what it designed and what it changed, and then the one thing it would not decide for you — which antenna — as a question with a recommendation, scoped to that part and nothing else.

The thread column: the prompt, the model's one-line summary of the board, and the build log — eighteen stages each with a tick and the seconds it took, from Thinking at 1m 02s to Saving v002. The model's reply: what it designed, what it revised after the ERC error, one gap reported, passes the build's check — then a card asking which antenna, with the integrated PCB antenna recommended.
the thread · gemini-3.8-flash · 18 steps · 1m 47s

02 · the workbench

Then it is yours.

The board on the stage and nothing floating over it. Drag a part and it is pinned; R turns it, F sends it to the back, X routes a net by hand as a constraint the next build keeps. The thread on the left, the picked part on the right — the ESP32 module here, its point cloud, its price and its 32,000 in stock — and the verdict underneath.

The whole workbench: the thread and build log on the left, the routed two-layer board on the stage with the ESP32 module picked, the part's card with its point cloud, price, stock and pins on the right, and the detail region with the price and the findings below.
the workbench · CU view · U1 picked · 55 × 37 mm, 2 layers

03 · the scope

Switched on before it is placed.

ngspice on the resolved netlist, before any copper exists: the declared rails stepped on and every net traced for ten milliseconds. Here +3V3 settles at 3.282 V against the 3.3 declared and the power LED draws 3.85 mA. The status LED hangs on the module, which has no SPICE model, so the scope says so rather than drawing a line it cannot stand behind.

The oscilloscope tab: voltage against time for ten nets over ten milliseconds, +3V3 picked and drawn in the accent, settling at 3.28 volts under VBUS at 5.
the scope · ngspice 45.2 · 10 nets · +3V3 as the probe

04 · the chain

Every stage is a device.

Design, resolve, simulate, place, route, pour, check, fab, price — as a chain, each box saying what it came back with: six placements rated, the A* router in one attempt, freerouting closing the one net it left, KiCad’s DRC clean. Above it the rack: router, seed, pour, precedent, track floor, sides, outline. Turn a knob and place again, or route again, without another word to the model.

The chain tab: seven knobs in a rack — router, seed, pour, precedent, floor, sides, outline — above nine device boxes from Design to Price, each with its seconds and what it produced.
the chain · v002 · built in 1m 47s

05 · the verdict

Passed — and 26 things it does not guarantee.

The verdict is the evaluator’s own rule, so the word on screen and the number on the benchmark cannot drift. Beside it, everything the build could not do, itemised: the module the simulation had no model for, two footprints taken from the vendor unverified, two pads that meet the ground pour by one thermal spoke where KiCad wants two. And the price at one, ten, twenty-five and a hundred, against live stock.

The detail region: the build's price at one board with each part's need, stock and runs on the left; on the right the findings — Verdict clean, Electrical 4 warnings, Routing 1 warning and 1 note, Stock clean, and Not guaranteed open with its gap and notes.
the detail · verdict clean · 1 warn · 25 notes · $21.76 / 1

06 · the board

As the fab will make it.

Every part wears the vendor’s own 3D model, turned to stand on its pads — the build measured which way each model faces and says so in the notes. What leaves as Gerbers, drill, BOM and placement files is this board. The hero is the same prompt built the day before, rendered by KiCad from its files.

The 3D view: the green two-layer board at an angle with the ESP32 module, USB-C receptacle, pin header, regulator and passives as vendor models, and the soldermask mark in the corner.
the 3D view · the vendor’s model on all 13 part lines

systems

Three systems ask the question, each earlier than the last.

ISOnet after a placement is made, Quorra while it is made, Mendicant before.

ISOnet

a network that learns the router’s verdict

A 32×32 congestion grid in, the router’s verdict out. AUC 0.916 held out. It reads board difficulty, not one board’s own anneals — so it ranks candidates, and does not steer the placer.

Open the thread

Quorra

a placer that listens to the judge

Not a new optimiser — a stricter judge for the annealer we had. It found the edge defect that left a fifth of placements unroutable. Fixed, the placer matches a person’s placement on 705 open-hardware boards; its best of six is ahead.

Open the thread

Mendicant

a board, read as a molecule

Pins on a circle, nets as chords, a crossing wherever two nets cannot share a layer: a board folded like RNA. The first signal that moves within one board. On a photonic chip, where a crossing is a device, it routes a 287-net mesh with none.

Open the thread

measured

Six numbers, each with what qualifies it.

37 / 59 benchmark prompts that build, unaided, to a board that passes every check Replayed 16 Sep 2026 and scored under the pass rule fixed that night (39 under the old one). With the wiring turn on — not yet the default — 40 of 59 on 15 Sep, nine boards gained and one lost against its same-day control, p = 0.02.
17–31 s saved design to fab files — parts, placement, routing, pour, DRC, Gerbers, price — on four boards Ten cores, 15 Sep 2026; the model’s design turn is not in it. The same boards had taken 83 to 140 s.
76.2 / 70.5 clean-route rate, A* at 0.127 mm and freerouting at 0.15, on 5,400 held-out placements of 1,350 boards Either router: 84%. KiCad’s DRC, 13 Sep 2026. At the old 0.25/0.2 convention: 67.8 and 63.0 — the rule was worth as much as the second router.
74.5 / 74.8 the placer’s first anneal against the person’s own placement, routed clean, on 705 open-hardware boards Best of six anneals: 80.4%. freerouting 2.4.1, 5 Sep 2026. The 14.5-point human lead we had published was a defect in our own placer.
0.916 the shipped model’s AUC on 14,089 held-out placements of 3,706 boards — 0.914 on PCBench Fitted 14 Sep 2026. Of 2,215 held-out boards with a clean option it picked one on 2,024; wirelength, 1,968. Within one board, 0.586.
63,644 router verdicts kept — the board as the router met it, and what it said — on 15,947 real boards Counted 15 Sep 2026, from a bank of 16,485 two-layer designs and 1,749 multilayer. PCBench’s 843 held aside as an external test, by content, not by path.

principles

How the lab works.

The router is the only judge

Not a model’s confidence, not a placement’s symmetry. Whether the router closes every net and the DRC finds nothing is the one test, asked of everything upstream.

A result is only as honest as the corpus behind it

A label defect sat in a quarter of the corpus until we went looking. A score that fails an audit is withdrawn in place, the day it is found.

Complexity has to earn its place

Every model is measured against the plainest baseline that could replace it, and often loses. What ships is whichever wins.

Every stage says what it could not do

A missing part is reported. An undriven rail is said out loud. A router that gives up says so. Silence costs a fab run to find out.

The board seen from low and to one side, its header pins standing up against the black.

next

Every number here is one router run from being wrong.

We would rather find that out than defend it. Next: the corpus, released with its split hash, so the claims can be checked by someone who did not make them.

Open the build