cadence

Since the first commit on 1 September 2026.

Counted from the tree on 15 September. The log is the primary record; everything here is in it with its date.

the works

What exists.

1. The pipelineA prompt to a fab-ready two-layer board: parts from live stock, ERC, simulation, placement on both sides, two routers, a poured ground, KiCad’s DRC, Gerbers, assembly files, a price — and a verdict. One build sequence behind the command line, the app and the evaluator.
2. The buildThe same board as a point cloud, ten acts, full screen — every number read off the frame.
3. The workbenchA browser app around the build: drag a part, pin it, route a net by hand, place again or route again from where you are, and an oscilloscope on the simulated circuit. The designer stays in control.
4. The corpus and the bankEvery route ever run, kept — 63,644 verdicts on 15,947 boards — drawn from a bank of 18,234 real designs read from KiCad, Eagle and Altium files. PCBench held aside as an external test by content, not by path.
5. ISOnetA network that learns the router’s verdict from a 32×32 congestion grid. AUC 0.916 held out; audited, and honest about what it reads — board difficulty, not one board’s own anneals.
6. QuorraA stricter judge for the annealer. It found the edge defect that left a fifth of placements unroutable; fixed, the placer matches a person on 705 open-hardware boards.
7. MendicantA board folded like RNA, then a slime mould that reads how walled-in every pin is in an eighth of a second — its inner loop in Rust, to floating-point noise of the numpy it replaces. Written up, reviewed twice.
8. Two routers, one judgeAn A* router first, freerouting as the second opinion, KiCad’s DRC as the only verdict; the rule tuned by experiment — 5,400 placements, four rules, two routers — before it shipped.
9. The evaluatorSixty prompts in four tiers, replayed through the one build path; the number a user sees and the number the harness measures cannot drift.
10. The parts resolverA parametric index over 242,213 typed attributes of the JLCPCB catalogue: 3.6 ms a lookup where full-text search took 537, and 99% correct at the top where it was 61%.
11. The reviewer’s rules82 rules a professional reviewer would apply. The 15 the pipeline can measure grade every build; the rest are named as unchecked rather than passed over.
12. The fold, on a chipMendicant’s fold pointed at a photonic integrated circuit, where a crossing is a device: a 287-net mesh routed with none, against a published 95.05%.
13. The retroThe first ten days, by the hour.

where it is going

The open problems, in the order they are being worked.

1. Ordering a board’s own placementsEvery judge here reads board difficulty; none yet orders one board’s anneals well enough to steer the placer. The model sits at 0.586, a judge earns its place at about 0.79, and the label permits 0.837 — so the signal is there and the estimators tried so far have not found it. This is the research problem.
2. The front halfThe benchmark loses most of its boards before the router: a part that resolves to the wrong thing, a rail nothing drives, a connection the prompt implied and the design dropped. The wiring turn took 32 to 40 of 59 (rescored 16 Sep; 33 to 40 as first logged) and is not yet the default.
3. The corpus, releasedWith its split hash, so the claims can be checked by someone who did not make them.
4. Four layers1,749 multilayer boards are in the bank and the model is two-layer by construction. The layer count is a scalar; the labels are not written.
5. LightThe fold on photonic chips is the second line of work, chosen on 15 September 2026. A crossing there is not a via but a device, and the placer that leads that field counts them by sampling.
6. The designer in controlEvery lever the pipeline has — pin, route by hand, place again, route again, the rack of seven knobs — is meant to be pulled from the workbench, not the command line. The workbench is where the next weeks go.